The present invention relates to integrated circuits (IC), and more particularly to controlling the power consumption and performance of ICs.
Much of the effort in the development of integrated circuits has been directed towards increasing speed and decreasing size. The optimization of circuit speed has often come at the expense of other factors, such as power consumption.
The increasing use of integrated circuits in electronic equipment and handheld device has seen a parallel rise in demand for increasing the energy efficiency and reducing power consumption of the integrated circuits. The growth in demand for battery-operated portable electronic devices, such as cellular phones or personal organizers, has brought to the fore the dual requirements of reducing the power consumption while maintaining or enhancing operational performance of the integrated circuits (hereinbelow, alternatively referred to as chip) disposed in such devices. Efforts to reduce power consumption and enhance performance should not result in a significant increase in development or manufacturing costs. Currently, the requirement for lower power consumption is driven either by cost in order to accommodate the chip in a cheaper package, or by the market forces requiring compliance with the Energy Star specifications. Chips targeting hand-held markets need to consume relatively very low power both in the idle mode and in operation so as to extend the battery lifetime.
Low power VLSI design is important for the dual purposes of reducing the power consumption and power dissipation. Power consumption and power dissipation are two different facets of the same phenomenon. Minimizing power consumption is necessary to extend the battery life in mobile applications, while minimizing power dissipation is important to ensure reliable device operation and use of cheaper packages.
The need for low-power design is also becoming a factor in high-performance digital systems, such as microprocessors and digital signal processors (DSP's) that operate at relatively high frequencies. Typically, the power dissipation of an IC, and its temperature increase linearly with the clock frequency. The dissipated heat must be directed away from the chip to keep its temperature at an acceptable level. Therefore, the packaging, cooling and heat removal are all factors that contribute to the cost.
Low power consumption has many advantages for non-portable products as well. For example, lowering the power consumption, enables the use of cheaper and lighter power supplies, less expensive IC packages, and simpler power distribution networks. Conventional power management techniques are generally directed to idle states. Once in an idle state, an IC or system may be placed in a sleep or standby mode, or alternatively may be switched off. While in such a mode, for each application that is running, a minimum performance level may be set in the Operating System (OS), to maintain the expected Quality of Service (QoS).
Efforts directed at achieving low power consumption in, for example, digital systems span a wide range of techniques, from device/process techniques to algorithm techniques. Device characteristics (e.g., threshold voltage), device geometries and interconnect properties are significant factors in lowering the power consumption. Circuit-level techniques, such as reducing the voltage swing or clocking strategies, can be used to reduce power dissipation at the transistor level. Architectural techniques include smart power management of various system blocks, utilization of pipelining and parallelism, and design of bus structures. The power consumed by the system may be reduced by the proper selection of the data processing algorithms to minimize the number of switching events for a given task.
Existing power management techniques typically focus on the Operating System (OS), firmware, and monitoring of the data activity and performance. Such techniques are generally closed-loop and require continuous adjustment during operation. In accordance with the well known Dynamic Frequency Scaling (DFS) technique, the frequency of the voltage island, or islands is/are reduced. DFS reduces peak power and thus enables the use of cheaper packages. In accordance with the well known Dynamic Voltage and Frequency Scaling (DVFS) technique, both the frequency and applied voltage are reduced. The DVFS technique reduces power consumption which has a quadratic relationship with the applied voltage. The DVFS is normally applied in a closed-loop manner by monitoring the data activity and other processes in real time and adapting the applied voltage to improve performance. Both DFS and DVFS techniques require changes in the frequency and thus can not be used in ICs required to operate at a certain frequency. In other words, neither DFS or DVFS can be used in ICs that are required to operate at a given frequency.
U.S. Pat. No. 7,240,223 appears directed at a dynamic power management technique using an operating system (OS) that causes a processor to operate in one of multiple run states with different performance and/or power dissipation levels. The OS selects the run state in response to processor information (e.g., processor load) being monitored by the OS. The OS can (i) predict future states of the processor information based on sampled processor information, (ii) take an average of the predicted and actual samples for comparison with a threshold to select a run state, (iii) track the number of consecutive saturated samples that occur during a selected window of samples, and (iv) predict future processor information samples based on the number of consecutive saturated samples.
U.S. Pat. No. 6,845,456 appears directed at a computer system that has multiple performance states. The system periodically obtains utilization information for a multitude of tasks running on the processor and determines processor utilization according to the utilization information for the tasks. The system compares the processor utilization to at least one threshold and selectively adjusts the processor performance according to the comparison result.
U.S. Pat. No. 7,230,602 appears directed at a source driver having a logic speed monitoring unit, an internal logic voltage generator, a substrate voltage generator, a substrate leakage-current monitoring unit, and a power management control unit for adjusting voltage using the speed data. By monitoring the logic operation speed of an internal logic circuit in the source driver, in accordance with the change of the operation frequency, the power is dynamically adjusted so as to optimize the power consumption and the operation speed. In the standby mode, adjusting the substrate voltage further reduces the power consumption. The substrate voltage can also be adjusted according to the substrate leakage current of the source driver.
U.S. Pat. No. 6,519,707 appears directed at a system that includes a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory stores processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and adjustment of the operating voltage of the processor based on the dynamic changes in the processing load of the processor and traffic changes.
U.S. Pat. No. 7,100,058 appears directed at a programmable power management integrated circuit that includes analog input monitors that receive analog input signals corresponding to voltage, current, or temperature measurements. The programmable logic device controls FET drivers that can turn on/off the power applied to the monitored system. The programmable power management integrated circuit may also include an internal oscillator, a serial interface, an in-system programmable interface, a JTAG interface, a memory that stores identification information, and a register for capturing system information during power-down. The applied power is not adjusted and is instead either turned on or turned off.
U.S. Pat. No. 7,117,378 appears directed at a digital circuit that includes a digital processing component, and power supply adjustment circuitry. The digital processing component is capable of operating at a number of clock frequencies. The maximum delay time of a critical path in the digital processing component is determined by the level of supplied voltage. The power supply adjustment circuitry is operable to receive a first clock signal and adjust the level of the supplied voltage such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first clock signal and a second clock edge of the first clock signal immediately following the first clock edge. The voltage is adjusted using a closed-loop technique.
U.S. Pat. No. 6,535,735 appears directed at maintaining the stability of a closed-loop system in which process variation is handled by assuming a worst case propagation delay of the critical path, and designing the clock frequency and minimum power supply voltage of the circuit to ensure proper operation under worst case conditions. Instead of assuming a worst case propagation delay of the critical path, the propagation delay may be measured in an actual circuit path that has been constructed to be the equivalent to, or slightly worse than, the propagation delay of the critical path. By knowing the actual worst case propagation delay, the circuit may be modified to operate with lower power supply voltages or have its clock frequency operate at or near the circuit's actual worst case limit. Such modifications of power supply voltage and/or clock frequency may occur during circuit operation and adapt to the different operating parameters of each circuit.
U.S. Pat. No. 7,061,292 appears directed at a system that includes a device having a critical path delay, a control logic responsive to output from the path delay and operative to generate a controlled output, and a power converter operative to adjust the supply voltage in response to the generated controlled output. The critical path delay, the control logic, and the power converter cooperate to provide first order bang-bang control of the critical path delay.
U.S. Pat. No. 7,134,031 appears directed at a multi-processing system that measures the degree of parallelism achieved in executing program instructions, and uses this information to dynamically control the clock speeds and voltage levels applied to different processor cores in order to reduce the overall amount of energy consumed.
U.S. Patent Application Publication No. 2002/0083356 appears directed at a system that dynamically transitions a processor between two performance states, high performance and low power. Predetermined core clock frequency and supply voltage levels of the processor define each performance state. Transitioning the supply voltage while the processor is in the active mode and transitioning the frequency while the processor is in the sleep mode appears to reduce the processor latency.
As is well known, the statistical process parameters inherent in any IC manufacturing processes result in variations in the speed and performance of the IC. The speed distribution of the manufactured ICs has a nearly Gaussian distribution. The power specification is often determined by fast ICs which have the highest power dissipation. The performance specification, on the other hand, is determined by the slow ICs which often have the lowest power dissipation. The spread between the slow and fast ICS, referred to as the performance gap, is widening as the drive toward sub-micron processing technologies continues.